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18Mb Pipelined DDRTMII SIO SRAM Burst of 2
Features

IDT71P79204 IDT71P79104 IDT71P79804 IDT71P79604
Description
The IDT DDRIITM Burst of two SIO SRAMs are high-speed synchronous memories with independent, double-data-rate (DDR), read and write data ports with two data items passed with each read or write. Using independent ports for read and write data access, simplifies system design by eliminating the need for bi-directional buses. All buses associated with the DDRII SIO are unidirectional and can be optimized for signal integrity at very high bus speeds. Memory bandwidth is higher than DDR SRAM with bi-directional data buses as separate read and write ports eliminate bus turn around cycle. Separate read and write ports also enable easy depth expansion. Each port can be selected independantly with a R/W input shared among all SRAMs and provide a new LD load control signal for each bank. The DDRII SIO has scalable output impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance. The DDRII SIO has a single SDR address bus with multiplexed read and write addresses. The read/write and load control inputs are received on the first half of the clock cycle. The byte and nibble write signals are received on both halves of the clock cycle simultaneously with the data they are controlling on the data input bus. The DDRII SIO has echo clocks, which provide the user with a clock that is precisely timed to the data output, and tuned with matching impedance and signal quality. The user can use the echo clock for downstream clocking of the data. Echo clocks eliminate the need for the user to produce alternate clocks with precise timing, positioning, and signal qualities to guarantee data capture. Since the echo clocks are
18Mb Density (2Mx8, 2Mx9, 1Mx18, 512Kx36) Separate, Independent Read and Write Data Ports - Supports concurrent transactions Dual Echo Clock Output 2-Word Burst on all SRAM accesses Multiplexed Address Bus - One Read or one Write request per clock cycle DDR (Double Data Rate) Data Bus - Two word burst data per clock Depth expansion through Control Logic HSTL (1.5V) inputs that can be scaled to receive signals from 1.4V to 1.9V. Scalable output drivers - Can drive HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V. - Output Impedance adjustable from 35 ohms to 70 ohms 1.8V Core Voltage (VDD) 165-ball, 1.0mm pitch, 15mm x 17mm fBGA Package JTAG Interface
Functional Block Diagram
(Note1) D DATA REG DATA REG (Note1)
WRITE DRIVER SA
LD R/W BWx
(Note3)
CTRL LOGIC
18M MEMORY ARRAY
(Note4)
(Note4)
OUTPUT SELECT
(Note2)
SENSE AMPS
OUTPUT REG
ADD REG
(Note2)
WRITE/READ DECODE
(Note1)
Q
K K C C
CLK GEN SELECT OUTPUT CONTROL
CQ CQ
6432 drw 16 Notes: 1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36 2) Represents 20 address signal lines for x8 and x9, 19 address signal lines for x18, and 18 address signal lines for x36. 3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a "nibble write" and there are 2 signal lines. 4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.
1
NOVEMBER 2005
(c)2005 Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.DSC-6432/01
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit) 18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
generated by the same source that drives the data output, the relationship to the data is not significantly affected by voltage, temperature and process, as would be the case if the clock were generated by an outside source. All interfaces of the DDR II SIO are HSTL, allowing speeds beyond SRAM devices that use any form of TTL interface. The interface can be scaled to higher voltages (up to 1.9V) to interface with 1.8V systems if necessary. The device has a VDDQ and a separate Vref, allowing the user to designate the interface operational voltage, independent of the device core voltage of 1.8V VDD. The output impedance control allows the user to adjust the drive strength to adapt to a wide range of loads and transmission lines. Clocking The DDRII SIO SRAM has two sets of input clocks, namely the K, K clocks and the C, C clocks. In addition, the DDRII SIO has an output "echo" clock, CQ, CQ. The K and K clocks are the primary device input clocks. The K clock is, used to clock in the control signals (LD, R/W and BWx or NWx), the address, and the first word of the data burst during a write operation. The K clock is used to clock in the control signals (BWx or NWx) and the second word of the data burst during a write operation. The K and K clocks are also used internally by the SRAM. In the event that the user disables the C and C clocks, the K and K clocks will also be used to clock the data out of the output register and generate the echo clocks. The C and C clocks may be used to clock the data out of the output register during read operations and to generate the echo clocks. C and C must be presented to the SRAM within the timing tolerances. The output data from the DDRII SIO will be closely aligned to the C and C input, through the use of an internal DLL. When C is presented to the DDRII SIO SRAM, the DLL will have already internally clocked the data to arrive at the device output simultaneously with the arrival of the C clock. The C and second data item of the burst will also correspond. Single Clock Mode The DDRII SIO SRAM may be operated with a single clock pair. C and C may be disabled by tying both signals high, forcing the outputs and echo clocks to be controlled instead by the K and K clocks. DLL Operation The DLL in the output structure of the DDRII SIO SRAM can be used to closely align the incoming clocks C and C with the output of the data, generating very tight tolerances between the two. The user may disable the DLL by holding Doff low. With the DLL off, the C and C (or K and K if C and C are not used) will directly clock the output register of the SRAM. With the DLL off, there will be a propagation delay from the time the clock enters the device until the data appears at the output. Echo Clock The echo clocks, CQ and CQ, are generated by the C and C clocks (or K, K if C, C are disabled). The rising edge of C generates the rising edge of CQ, and the falling edge of CQ. The rising edge of C generates the rising edge of CQ and the falling edge of CQ. This scheme improves
the correlation of the rising and falling edges of the echo clock and will improve the duty cycle of the individual signals. The echo clock is very closely aligned with the data, guaranteeing that the echo clock will remain closely correlated with the data, within the tolerances designated. Read and Write Operations DDRII SIO devices internally store the two words of the burst as a single wide word and the words will retain their burst order. There is no ability to address an individual word level in a burst, as is possible in the DDRII common I/O devices. The byte and nibble write signals can be used to prevent writing to any individual bytes, or combined to prevent writing word(s) of the burst. Read operations are initiated by holding Read/Write control input (R/W) high, the load control input (LD) low and presenting the read address to the address port during the rising edge of K, which will latch the address. The data will then be read and will appear at the device output at the designated time in correspondence with the C and C clocks. Write operations are initiated by holding the Read/Write control input (R/W) low, the load control input (LD) low and presenting the write address to the address port during the rising edge of K, which will latch the address. On the following rising edge of K, the first word of the two word burst must be present on the data input bus DQ[x:O], along with the appropriate byte write or nibble write (BWx or NWx) inputs. On the following rising edge of K, the second half of the data write burst will be accepted at the device input with the designated (BWx or NWx) inputs. Output Enables The DDRII SIO SRAM automatically enables and disables the Q[X:0] outputs. When a valid read is in progress, and data is present at the output, the output will be enabled. If no valid data is present at the output (read not active), the output will be disabled (high impedance). The echo clocks will remain valid at all times and cannot be disabled or turned off. During power-up the Q outputs will come up in a high impedance state. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and Vss to allow the SRAM to adjust its output drive impedance. The value of RQ must be 5X the value of the intended drive impedance of the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of +/- 10% is between 175 ohms and 350 ohms, with VDDQ = 1.5V. The output impedance is adjusted every 1024 clock cycles to correct for drifts in supply voltage and temperature. If the user wishes to drive the output impedance of the SRAM to it's lowest value, the ZQ pin may be tied to VDDQ.
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IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit) 18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
Pin Definitions
Symbol Pin Function Description Data input signals, sampled on the rising edge of K and K clocks during valid write operations 2M x 8 -- D[7:0] 2M x 9 -- D[8:0] 1M x 18 -- D[17:0] 512K x 36 -- D[35:0] Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising edge of K clocks during write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written in to the device. 2M x 9 -- BW0 controls DQ[8:0] 1M x 18 -- BW0 controls DQ[8:0] and BW1 controls DQ[17:9] 512K x 36 -- BW0 controls DQ[8:0], BW1 controls DQ[17:9], BW2 controls DQ[26:18] and BW3 controls DQ[35:27] Nibble Write Select 0 and 1 are active LOW. Available only on x8 bit parts instead of Byte Write Selects. Sampled on the rising edge of the K and K clocks during write operations. Used to select which nibble is written into the device during the current portion of the write operations. Nibbles not written remain unaltered. All the nibble writes are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause the corresponding nibble of data to be ignored and not written in to the device. 2M x 8--NW0 controls D[3:0] and NW1 controls D[7:4] Address Inputs. Addresses are sampled on the rising edge of K clock during active read or write operations. Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when operating in single clock mode. When the Read port is deselect ed, Q[X:0] are automatically three-stated. Load Control Logic. Sampled on the rising edge of K. If LD is low, a two word burst read or write operation will be initiated as designated by the R/W input. If LD is high during the rising edge of K, operations in progress will complete, but new operations will not be initiated. Read or Write Control Logic. If LD is low during the rising edge of K, the R/W indicates whether a new operation should be a read or write. If R/W is high, a read operation will be initiated, if R/W is low, a write operation will be initiated. If the LD input is high during the rising edge of K, the R/W input will be ignored. Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[X:0] when in single clock mode. All accesses are initiated on the rising edge of K. Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[X:0] when in single clock mode. Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals are free running and do not stop when the output data is three stated. Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q[X:0] output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
6432 tbl 02a
D[X:0]
Input Synchronous
BW0, BW1 BW2, BW3
Input Synchronous
NW0 NW1
Input Synchronous
SA
Input Synchronous Output Synchronous Input Synchronous Input Synchronous
Q[X:0]
LD
R/W
C
Input Clock
C
Input Clock
K K
Input Clock Input Clock
CQ, CQ
Output Clock
ZQ
Input
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IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit) 18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
Pin Definitions continued
Symbol Pin Function Description DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the DLL turned off will be different from those listed in this data sheet. There will be an increased propagation delay from the incidence of C and C to Q, or K and K to Q as configured. The propagation delay is not a tested parameter, but will be similar to the propagation delay of other SRAM devices in this speed grade. TDO pin for JTAG. TCK pin for JTAG. TDI pin for JTAG. An internal resistor will pull TDI to VDD when the pin is unconnected. TMS pin for JTAG. An internal resistor will pull TMS to VDD when the pin is unconnected. No connects inside the package. Can be tied to any voltage level. Input Reference Power Supply Ground Power Supply Reference Voltage input. Static input used to set the reference level for HSTL inputs and Outputs as well as AC measurement points. Power supply inputs to the core of the device. Should be connected to a 1.8V power supply. Ground for the device. Should be connected to ground of the system. Power supply for the outputs of the device. Should be connected to a 1.5V power supply for HSTL or scaled to the desired output voltage.
6432 tbl 02b
Doff
Input
TDO TCK TDI TMS NC VREF VDD VSS VDDQ
Output Input Input Input
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IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit) 18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
Pin Configuration IDT71P79204 (2M x 8)
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO 2 VSS/ SA (2) NC NC D4 NC NC D5 VREF NC NC Q6 NC D7 NC TCK 3 SA NC NC NC Q4 NC Q5 VDDQ NC NC D6 NC NC Q7 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 NW1 NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC NW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 VSS/ SA (1) NC NC NC D2 NC NC VREF Q1 NC NC NC NC NC TMS 11 CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC NC TDI
6432 tbl 12
165-ball FBGA Pinout TOP VIEW
NOTES: 1. A10 is reserved for the 36Mb expansion address. 2. A2 is reserved for the 72Mb expansion address.
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IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit) 18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
Pin Configuration IDT71P79104 (2M x 9)
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO 2 VSS/ SA (2) NC NC D4 NC NC D5 VREF NC NC Q6 NC D7 NC TCK 3 SA NC NC NC Q4 NC Q5 VDDQ NC NC D6 NC NC Q7 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 NC NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC BW SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 VSS/ SA (1) NC NC NC D2 NC NC VREF Q1 NC NC NC NC D8 TMS 11 CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC Q8 TDI
6432 tbl 12a
165-ball FBGA Pinout Top View
NOTES: 1. A10 is reserved for the 36Mb expansion address. 2. A2 is reserved for the 72Mb expansion address.
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IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit) 18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
Pin Configuration IDT71P79804 (1M x 18)
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO 2 VSS/ SA(3) Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK 3 NC/ SA(1) D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW1 NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 VSS/ SA(2) NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
6432 tbl 12b
165-ball FBGA Pinout Top View
NOTES: 1. A3 is reserved for the 36Mb expansion address. 2. A10 is reserved for the 72Mb expansion address. This must be tied or driven to VSS on the 1M x 18 DDRII SIO Burst of 2 (71P79804) devices. 3. A2 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 1M x 18 DDRII SIO Burst of 2 (71P79804) devices.
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IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit) 18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
Pin Configuration IDT71P79604 (512K x 36)
1 A B C D E F G H J K L M N P R CQ Q27 D27 D28 Q29 Q30 D30 Doff D31 Q32 Q33 D33 D34 Q35 TDO 2 VSS/ SA (4) Q18 Q28 D20 D29 Q21 D22 VREF Q31 D32 Q24 Q34 D26 D35 TCK 3 NC/ SA (2) D18 D19 Q19 Q20 D21 Q22 VDDQ D23 Q23 D24 D25 Q25 Q26 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW2 BW3 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 BW1 BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 NC/ SA (1) D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 SA 10 VSS/ SA (3) Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
6432 tbl 12c
165-ball FBGA Pinout TOP VIEW
NOTES: 1. A9 is reserved for the 36Mb expansion address. 2. A3 is reserved for the 72Mb expansion address. 3. A10 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 512K x 36 DDRII SIO Burst of 2 (71P79604) devices. 4. A2 is reserved for the 288Mb expansion address. This must be tied or driven to VSS on the 512K x 36 DDRII SIO Burst of 2 (71P79604) devices.
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IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit) 18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1) (2)
Symbol VTERM VTERM VTERM VTERM TBIAS TSTG IOUT Rating Supply Voltage on VDD with Respect to GND Supply Voltage on VDDQ with Respect to GND Voltage on Input terminals with respect to GND Voltage on output and I/O terminals with respect to GND Temperature Under Bias Storage Temperature Continuous Current into Outputs Value -0.5 to +2.9 -0.5 to VDD+0.3 -0.5 to VDD +0.3 -0.5 to VDDQ +0.3 -55 to +125 -65 to +150 + 20 C C mA
6432 tbl 05
Capacitance (TA = +25C, f = 1.0MHz)(1)
Unit V V V
Symbol CIN CCLK CO Parameter Input Capacitance Clock Input Capacitance Output Capacitance VDD = 1.8V VDDQ = 1.5V Conditions Max. 5 6 7 Unit pF pF pF
6432 tbl 06
Note: 1. Tested at characterization and retested after any design or process change that may affect these parameters.
Recommended DC Operating Conditions
Symbol VDD VDDQ VSS VREF TA Parameter Power Supply Voltage I/O Supply Voltage Ground Input Reference Voltage Ambient Temperature (1) Commercial Industrial Min. 1.7 1.4 0 Typ. 1.8 1.5 0 VDDQ/2 0 to +70 -40 to +85 Max. 1.9 1.9 0 Unit V V V V
o
Notes: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDDQ must not exceed VDD during normal operation.
c c
o
Write Descriptions(1,2)
Signal Write Byte 0 Write Byte 1 Write Byte 2 Write Byte 3 Write Nibble 0 Write Nibble 1 BW0 L X X X X X BW1 X L X X X X BW2 X X L X X X BW3 X X X L X X NW0 X X X X L X NW1 X X X X X L
6432 tbl 09
Note: 1. During production testing, the case temperature equals the ambient temperature.
6432 tbl 04
Notes: 1) All byte write (BWx) and nibble write (NWx) signals are sampled on the rising edge of K and again on K. The data that is present on the data bus\ in the designated byte/nibble will be latched into the input if the corresponding BWx or NWx is held low. The rising edge of K will sample the first byte/nibble of the two word burst and the rising edge of K will sample the second byte nibble of the two word burst. 2) The availability of the BWx or NWx on designated devices is described in the pin description table. 3) The DDRII SIO Burst of two SRAM has data forwarding. A read request that is initiated on cycle following a write request to the same address will produce the newly written data in response to the read request.
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IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit) 18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
Application Example
SRAM #1 D SA LD R/W BW0 BW1 C C ZQ Q KK 250
SRAM #4
VT R Data In Data Out Address LD R/W BWx/NWx MEMORY CONTROLLER Return CLK Source CLK Return CLK Source CLK
D SA LD R/W BW0 BW1 C C
ZQ Q KK
R R R R R
250
VT
VT VT R R
R = 50
VT = VREF
6432 drw 20
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IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit) 18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 1.8 100mV, VDDQ = 1.4V to 1.9V)
Parameter Input Leakage Current Output Leakage Current Symbol IIL IOL Test Conditions VDD = Max VIN = VSS to VDDQ Output Disabled Min -2 -2 Com'l Operating Current (x36): DDR VDD = Max, IOUT = 0mA (outputs open), Cycle Time > tKHKH Min 250MHZ 200MHz 167MHz 267MHz Operating Current (x18): DDR IDD VDD = Max, IOUT = 0mA (outputs open), Cycle Time > tKHKH Min 250MHZ 200MHz 167MHz Operating Current (x9,x8): DDR VDD = Max, IOUT = 0mA (outputs open), Cycle Time > tKHKH Min 250MHZ 200MHz 167MHz 267MHz Standby Current: NOP ISB1 Device Deselected (in NOP state) IOUT = 0mA (outputs open), f=Max, All Inputs <0.2V or > VDD -0.2V RQ = 250, IOH = -15mA RQ = 250, IOL = 15mA IOH = -0.1mA IOL = 0.1mA 250MHZ 200MHz 167MHz Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage VOH1 VOL1 VOH2 VOL2 VDDQ/2-0.12 VDDQ/2-0.12 VDDQ-0.2 VSS 1050 950 850 950 850 750 650 800 700 600 420 375 335 300 Max +2 +2 Ind 1100 1000 900 980 900 mA 800 700 850 750 650 450 410 mA 370 335 V V V V 3,7 4,7 5 6 2 mA 1 1 mA 1 Unit uA uA Note
IDD
IDD
VDDQ/2+0.12 VDDQ/2+0.12 VDDQ 0.2
6432 tbl 10c NOTES: 1. Operating Current is calculated with 50% read cycles and 50% write cycles. 2. Standby Current is only after all pending read and write burst operations are completed. 3. Outputs are impedance-controlled. IOH = -(VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175 < RQ < 350. This parameter is tested at RQ = 250, which gives a nominal 50 output impedance. 4. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175 < RQ < 350. This parameter is tested at RQ = 250, which gives a nominal 50 output impedance. 5. This measurement is taken to ensure that the output has the capability of pulling to the VDDQ rail, and is not intended to be used as an impedance measurement point. 6. This measurement is taken to ensure that the output has the capability of pulling to Vss, and is not intended to be used as an impedance measurement point. 7. Programmable Impedance Mode.
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IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit) 18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
Input Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 1.8 100mV, VDDQ = 1.4V to 1.9V)
Parameter Input High Voltage, DC Input Low Voltage, DC Input High Voltage, AC Input Low Voltage, AC Symbol VIH (DC) VIL (DC) VIH (AC) VIL (AC) Min VREF +0.1 -0.3 VREF +0.2 Max VDDQ +0.3 VREF -0.1 VREF -0.2 Unit V V V V Notes 1,2 1,3 4,5 4,5
6432 tbl 10d NOTES: 1. These are DC test criteria. DC design criteria is VREF + 50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters. 2. VIH (Max) DC = VDDQ+0.3, VIH (Max) AC = VDD +0.5V (pulse width <20% tKHKH (min)) 3. VIL (Min) DC = -0.3V, VIL (Min) AC = -0.5V (pulse width <20% tKHKH (min)) 4. This conditon is for AC function test only, not for AC parameter test. 5. To maintain a valid level, the transitioning edge of the input must: a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC) b) Reach at least the target AC level. c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)
Overshoot Timing
20% tKHKH (MIN) VDD +0.5 VDD +0.25
Undershoot Timing
VIH
VSS
VDD
VSS-0.25V VSS-0.5V
VIL
6432 drw 22
6432 drw 21
20% tKHKH (MIN)
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IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit) 18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
AC Test Conditions
Parameter Core Power Supply Voltage Output Power Supply Voltage Input High Level Input Low Level Input Reference Level Input Rise/Fall Time Output Timing Reference Level
NOTE: 1. Parameters are tested with RQ=250
Symbol VDD VDDQ VIH VIL VREF TR/TF
Value 1.7-1.9 1.4-1.9 (VDDQ/2) + 0.5 (VDDQ/2) - 0.5 VDDQ/2 0.3/0.3 VDDQ/2
Unit V V V V V ns V
6432 tbl 11a
Input Waveform
(VDDQ/2) + 0.5V VDDQ/2 (VDDQ/2) - 0.5V
6432 drw 07
Test points
VDDQ/2
Output Waveform
VDDQ/2
Test points
VDDQ/2
6432 drw 08
AC Test Loads
VDDQ/2 VREF OUTPUT Device Under Test ZQ Z0 =50 RQ = 250 VDDQ/2 RL = 50
6432 drw 04
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IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit) 18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 1.8 100mV, VDDQ = 1.4V to 1.9V, Commercial and Industrial Temperature Ranges)(3,7)
267MHz Symbol Clock Parameters tKHKH tKC var tKHKL tKLKH tKHKH tKHKH tKHCH tKC lock tKC reset Clock Cycle Time (K,K,C,C) Clock Phase Jitter (K,K,C,C) Clock High Time (K,K,C,C) Clock LOW Time (K,K,C,C) Clock to clock (KK,CC) Clock to clock (KK,CC) Clock to data clock (KC,KC) DLL lock time (K, C) K static to DLL reset 3.75 1.50 1.50 1.69 1.69 0.00 1024 30 6.30 1.69 4.00 1.60 1.60 1.80 1.80 0.00 1024 30 6.30 0.20 1.80 5.00 2.00 2.00 2.20 2.20 0.00 1024 30 7.88 0.20 2.30 6.00 2.40 2.40 2.70 2.70 0.00 1024 30 8.40 0.20 2.80 ns ns ns ns ns ns ns cycles ns 2 1,5 8 8 9 9 Parameter Min. Max 250MHz Min. Max 200MHz Min. Max 167MHz Min. Max Unit Notes
Output Parameters tCHQV tCHQX tCHCQV tCHCQX tCQHQV tCQHQX tCHQZ tCHQX1 C,C HIGH to output valid C,C HIGH to output hold C,C HIGH to echo clock valid C,C HIGH to echo clock hold CQ,CQ HIGH to output valid CQ,CQ HIGH to output hold C HIGH to output High-Z C HIGH to output Low-Z -0.45 -0.45 -0.30 -0.45 0.45 0.45 0.30 0.45 -0.45 -0.45 -0.30 -0.45 0.45 0.45 0.30 0.45 -0.45 -0.45 -0.35 -0.45 0.45 0.45 0.35 0.45 -0.50 -0.50 -0.40 -0.50 0.50 0.50 0.40 0.50 ns ns ns ns ns ns ns ns 3,4,5 3,4,5 3 3 3 3
Set-Up Times tAVKH tIVKH tDVKH Address valid to K,K rising edge R/W inputs valid to K,K rising edge Data-in and BWx/NWx valid to K, K rising edge 0.50 0.50 0.35 0.50 0.50 0.35 0.60 0.60 0.40 0.70 0.70 0.50 ns ns ns 6
Hold Times tKHAX tKHIX tKHDX K,K rising edge to address hold K,K rising edge to R/W inputs hold K, K rising edge to data-in and BWx/NWx hold 0.50 0.50 0.35 0.50 0.50 0.35 0.60 0.60 0.40 0.70 0.70 0.50 ns ns ns 6
6432 tbl 11 NOTES: 1. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 2. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable. 3. If C,C are tied High, K,K become the references for C,C timing parameters. 4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worse case at totally different test conditions (0C, 1.9V) than tCHQZ, which is a MAX parameter (worst case at 70C, 1.7V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature. 5. This parameter is guaranteed by device characterization, but not production tested. 6. All address inputs must meet the specified setup and hold times for all latching clock edges. 7. During production testing, the case temperature equals TA. 8. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60% of the cycle time (tKHKH). 9. Clock to clock time (tKHKH) and Clock to clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH).
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IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit) 18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles
NOP 1 Read A0 (burst of 2) 2 Read A1 (burst of 2) 3 Write A2 Write A3 (burst of 2) (burst of 2) 4 5 Read A4 (burst of 2) 6 NOP 7 8
K
tKHKL tKLKH tKHKH tKHKH
K
LD
tIVKH tKHIX
R/W
A
A0
A1
A2
tKHDX
A3
A4
tKHDX tDVKH
tAVKH tKHAX
tDVKH
D
D20
D21
D30
D31
Q
Qx1
Q00
Q01
Q10
Q11
Q40
Q41
tCHQV tKHCH tKHCH tCHQV tCHQX tCHQX1
tCHQZ tCHQX
tCQHQV
C
tKHKL tKLKH tKHKH tKHKH
C
tCHCQV tCHCQX
CQ
tCHCQV tCHCQX
CQ
6432 drw 09a
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IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit) 18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port (TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up; therefore, the TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude a mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected, but they may also be tied to VDD through a resistor. TDO should be left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2 0 0 IR1 0 0 1 1 0 0 1 1 IR0 0 1 0 1 0 1 0 1 Instruction EXTEST IDCODE SAMPLE-Z RESERVED TDO Output Boundary Scan Register Identification register Boundary Scan Register Do Not Use 2 1 5 4 5 5 3
6432 tbl 13
Notes
A,D K,K C,C Q CQ CQ
0
SRAM CORE
0 1 1 1
SAMPLE/PRELOAD Boundary Scan register RESERVED RESERVED BYPASS Do Not Use Do Not Use Bypass Register
TDI
BYPASS Reg. Identification Reg. Instruction Reg. Control Signals
TDO
1
TMS TCK
TAP Controller
6432 drw 18
TAP Controller State Diagram
Test Logic Reset 1 0 Run Test Idle 0 1 1 Select DR 0 Capture DR 0 Shift DR 1 1 Exit 1 DR 0 Pause DR 1 Exit 2 DR 1 1 Update DR 0 0 0 1 1 1 Select IR 0 Capture IR 0 Shift IR 1 Exit 1 IR 0 Pause IR 1 Exit 2 IR 1 Update IR 1 0 1
NOTES: 1. Places Qs in Hi-Z in order to sample all input data regardless of other SRAM inputs. 2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 3. Bypass register is initialized to Vss when BYPASS instruction is invoked. The Bypass Register also holds serially loaded TDI when existing the Shift DR states. 4. SAMPLE instruction does not place output pins in Hi-Z. 5. This instruction is reserved for future use.
0
0
0 0
6432 drw 17
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IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit) 18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
Scan Register Definition
Part 512K x36 1Mx18 2Mx8/x9 Instrustion Register 3 bits 3 bits 3 bits Bypass Register 1 bit 1 bit 1 bit ID Register 32 bits 32 bits 32 bits Boundry Scan 107 bits 107 bits 107 bits
6432 tbl 14
Identification Register Definitions
INSTRUCTION FIELD Revision Number (31:29) ALL DEVICES 0x0 0x0298 0x0299 0x029A 0x029B 0x033 1 DESCRIPTION Revision Number 512Kx36 1Mx18 2Mx9 2Mx8 DDRII SIO BURST OF 2 71P79604S 71P79804S 71P79104S 71P79204S PART NUMBER
Device ID (28:12)
IDT JEDEC ID CODE (11:1) ID Register Presence Indicator (0)
Allows unique identification of SRAM vendor. Indicates the presence of an ID register.
6432 tbl 15
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IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit) 18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
Boundary Scan Exit Order
ORDER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PIN ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H 10G 9G 11F 11G 9F 10F 11E 10E
6432 tbl 16
ORDER 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PIN ID 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A Internal 9A 8B 7C 6C
ORDER 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
PIN ID 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R
6432 tbl 18
8A
89
7A 7B 6B 6A 5B 5A 4A 5C 4B 3A 1H 1A 2B 3B 1C 1B 3D 3C 1D
6432 tbl 17
90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107
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IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit) 18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
JTAG DC Operating Conditions
Parameter Output Power Supply Power Supply Voltage Input High Level Input Low Level TCK Input Leakage Current TMS, TDI Input Leakage Current TDO Output Leakage Current Output High Voltage (IOH = -1mA) Output Low Voltage (IOL = 1mA) Symbol VDDQ VDD VIH VIL IIL IIL IOL VOH VOL Min 1.4 1.7 1.3 - 0.3 -5 - 15 -5 VDDQ - 0.2 VSS Typ 1.8 Max 1.9 1.9 VDD + 0.3 0.5 +5 + 15 +5 VDDQ 0.2 Unit V V V V uA uA uA V V 1 1
6432 tbl 19
Note
NOTE: 1. The output impedance of TDO is set to 50 ohms (nominal process) and does not vary with the external resistor connected to ZQ.
JTAG AC Test Conditions
Parameter Input High Level Input Low Level Input Rise/Fall Time Input and Output Timing Reference Level Symbol VIH VIL TR/TF Min 1.8 0 1.0/1.0 0.9 Unit V V ns V 1
6432 tbl 20
Note
Note: 1. For SRAM outputs see AC test output load on page 13.
JTAG Input Test WaveForm
1.8 V 0.9 V 0V
6432 drw 23
JTAG AC Test Load
0.9 V
Test points
0.9 V
50ohm Z0 = 50ohm TDO
6109 drw 24
JTAG Output Test WaveForm
0.9 V Test points 0.9 V
6432 drw 23a
,
6.42 19
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit) 18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
JTAG AC Characteristics
Parameter TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TMS Input Setup Time TMS Input Hold Time TDI Input Setup Time TDI Input Hold Time SRAM Input Setup Time SRAM Input Hold Time Clock Low to Output Valid Symbol tCHCH tCHCL tCLCH tMVCH tCHMX tDVCH tCHDX tSVCH tCHSX tCLQV Min 50 20 20 5 5 5 5 5 5 0 Max 10 Unit ns ns ns ns ns ns ns ns ns ns
6432 tbl 21
Note
JTAG Timing Diagram
TCK TMS
tDVCH
tCHCH tMVCH
tCHCL tCHMX
tCLCH
tCHDX
TDI/ SRAM INPUTS SRAM OUTPUTS
tCLQV
tSVCH
tCHSX
TDO
6432drw 19
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IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit) 18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
Package Diagram Outline for 165-Ball Fine Pitch Grid Array
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IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit) 18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
Ordering Information
IDT XXX Device Type S Power XXX Speed BQ Package X Process/ Temperature Range
Blank I BQ
Commercial (0C to +70C) Industrial (-40C to +85C) 165 Fine Pitch Ball Grid Array (fBGA)
267* 250 200 167
Clock Frequency in MegaHertz
IDT71P79204 IDT71P79104 IDT71P79804 IDT71P79604
2M x 8 DDR II SIO SRAM 2M x 9 DDR II SIO SRAM 1M x 18 DDR II SIO SRAM 512K x 36 DDR II SIO SRAM 6432 drw 15
* Only offered in the x18 option.
CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2774 www.idt.com
for Tech Support: sramhelp@idt.com 800-345-7015 or 408-284-4555
The IDT logo is a registered trademark of Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.
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IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit) 18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
Revision History
REV 0 1 DATE 07/26/05 11/30/05 PAGES p. 1-21 p. 11,14,22 DESCRIPTION Released Final datasheet Added 267MHz speed grade to the DC and AC Electrical Characteristics tables and ordering information.
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